A Low-Power, Dual-Wavelength Photoplethysmogram (PPG) SoC With Static and Time-Varying Interferer Removal

This paper presents a low-power, reflectance-mode photoplethysmogram (PPG) front end with up to 100 μA of static interferer current removal and 87 dB attenuation of time-varying interferers. The chip nominally consumes 425 μW including signal chain circuits, red and IR LED drive power, clocks, digitization and I/O. Measured data shows the noise of the PPG signal to be dominated by the photodiode sensor photon shot noise.