InAs Nanowire Transistors with Multiple, Independent Wrap-Gate Segments.

Area of Science:

• Nanotechnology
• Materials Science
• Electrical Engineering

Background:

• Wrap-gate nanowire transistors are crucial for advanced electronic devices.
• Current fabrication methods for multiple wrap-gates, especially in vertical orientations, are complex and time-consuming.
• Scalability remains a challenge for integrating multiple gate segments in nanowire transistors.

Purpose of the Study:

• To present a novel fabrication method for horizontal wrap-gate nanowire transistors.
• To demonstrate the ability to create devices with up to four independently controllable wrap-gated segments.
• To highlight the scalability and efficiency advantages of the horizontal orientation.

Main Methods:

• Fabrication of horizontal wrap-gate nanowire transistors with multiple segments.
• Characterization of transistor performance, including gate control and crosstalk.
• Comparison of fabrication complexity with vertical wrap-gate designs.

Main Results:

• Successfully fabricated horizontal wrap-gate nanowire transistors with up to four independent segments.
• Demonstrated negligible crosstalk between adjacent gate segments (<200 nm separation).
• Showcased the ability to create multiple wrap-gate transistors on a single nanowire using a single process.

Conclusions:

• The horizontal wrap-gate orientation offers superior scalability for multi-segment nanowire transistors compared to vertical designs.
• This method simplifies the fabrication of complex nanowire devices, reducing manufacturing steps.
• The technology is promising for advanced nanowire applications and integration into 3D architectures.