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    This study introduces an efficient hardware architecture for cascade support vector machines (SVMs), accelerating image object detection. The novel design achieves real-time processing speeds and reduces resource utilization and power consumption.

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    Area of Science:

    • Computer Engineering
    • Machine Learning
    • Hardware Acceleration

    Background:

    • Support Vector Machines (SVMs) are computationally intensive for classification tasks.
    • Existing hardware architectures primarily support monolithic SVMs, not optimized cascade SVMs.
    • Cascade SVMs offer speedups for imbalanced datasets, common in image object classification.

    Purpose of the Study:

    • To propose and evaluate a hybrid processing hardware architecture for accelerating cascade SVM classification.
    • To develop methods for reducing hardware resource requirements and improving classification speed.
    • To demonstrate real-time object detection using the proposed architecture on an FPGA platform.

    Main Methods:

    • Designed a hybrid processing hardware architecture specifically for cascade SVMs.
    • Implemented a method to reduce hardware resource utilization.
    • Developed a technique to enhance classification speed by leveraging cascade information for data discarding.
    • Integrated a neural network to process cascade information for performance boost.
    • Deployed the architecture on a Spartan-6 FPGA for evaluation.

    Main Results:

    • Achieved a real-time processing rate of 40 frames/s for face detection on 800×600 images.
    • The hardware-reduction method decreased FPGA custom-logic resource usage by 25%.
    • Attained a 20% peak power reduction compared to a baseline implementation.
    • Demonstrated effective object detection capabilities.

    Conclusions:

    • The proposed hybrid hardware architecture significantly accelerates cascade SVMs for real-time applications.
    • The developed methods effectively reduce hardware resource and power consumption while enhancing speed.
    • This approach offers a practical solution for efficient SVM-based object detection on FPGAs.