Performance Investigation of Nanoscale Strained Ge pMOSFETs with a GeSn Alloy Stressor

A germanium (Ge)-based substrate combined with germanium-tin (GeSn) alloy embedded in source/drain (S/D) regions has attracted significant attention because of its ability to satisfy the requirements of a high-mobility channel. Devices are shrunk in their geometries to meet the target of superior density in layout arrangement. Thus, determining the influences of devices on mobility gain is important. Accordingly, several designed factors, including gate width, S/D length, and Sn concentration of the GeSn stressor, are systematically analyzed in this study. A second-order formula composed of piezoresistance coefficients is derived and adopted to achieve a precise mobility gain estimation. A peak of the carrier mobility gain appears when a nanoscale geometry combination of 20 nm gate length and -200 nm gate width is used in the Ge channel, and 10% of the Sn mole proportion of the GeSn alloy is applied.