Large-Area CVD-Grown Sub-2 V ReS₂ Transistors and Logic Gates

Area of Science:

• Materials Science
• Nanotechnology
• Electronics Engineering

Background:

• Two-dimensional (2D) materials offer unique electronic properties for next-generation devices.
• Rhenium disulfide (ReS2) is a promising 2D material with potential for electronic applications.
• Developing scalable fabrication methods for 2D materials is crucial for practical implementation.

Purpose of the Study:

• To demonstrate the fabrication of large-area ReS2 transistors and logic gates.
• To investigate the performance of ReS2 transistors utilizing graphene electrodes and ion gel gating.
• To assess the potential of these devices for complex logic circuits and flexible electronics.

Main Methods:

• Fabrication of multilayer ReS2 using chemical vapor deposition (CVD).
• Integration of single-layer graphene as source/drain and coplanar gate electrodes.
• Utilizing an ion gel electrolyte for efficient low-voltage gating (< 2 V).

Main Results:

• Achieved large-area synthesis of ReS2 semiconductor channels and graphene electrodes.
• Demonstrated ReS2 transistors with significantly reduced contact resistance using graphene electrodes.
• Exhibited high device performance: electron mobility up to 0.9 cm^2/(V s) and on/off ratio > 10^4.
• Successfully assembled NMOS logic gates (NOT, NAND, NOR) using the fabricated transistors.

Conclusions:

• The developed fabrication process enables large-area production of ReS2-based electronic components.
• Ion gel-gated ReS2 transistors with graphene electrodes show excellent performance characteristics.
• These findings highlight the viability of ReS2 and graphene for advanced logic circuits and flexible electronic applications.