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Related Experiment Video

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Compensation of PVT Variations in ToF Imagers with In-Pixel TDC.

Ion Vornicu1, Ricardo Carmona-Galán2, Ángel Rodríguez-Vázquez3

  • 1Instituto de Microelectrónica de Sevilla, IMSE-CNM (CSIC-Universidad de Sevilla), Avda. Américo Vespucio s/n, Parque Científico y Tecnológico de La Cartuja, Seville 41092, Spain. ivornicu@imse-cnm.csic.es.

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|May 10, 2017
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Summary
This summary is machine-generated.

This study introduces a compensation loop to stabilize direct time-of-flight complementary metal-oxide-semiconductor image sensor performance. The system-level design minimizes variations from process, voltage, and temperature (PVT) for accurate 3D ranging and depth imaging.

Keywords:
PVT compensationin-pixel time-to-digital converter (TDC)single-photon avalanche-diode (SPAD)time-gatingtime-of-flight (ToF)

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Area of Science:

  • * Solid-state device physics and integrated circuit design.
  • * Photonics and optical sensing technologies.

Background:

  • * Direct time-of-flight complementary metal-oxide-semiconductor image sensors (dToF-CIS) rely on single-photon avalanche diode (SPAD) arrays and in-pixel time-to-digital converters (TDCs).
  • * Sensor performance is significantly impacted by process parameters, voltage supply, and temperature (PVT) variations, leading to time bin drift in TDCs.
  • * Accurate 3D ranging and depth map imaging require stable and precise time measurements from these sensors.

Purpose of the Study:

  • * To analyze the impact of PVT variations on the time bin of TDC arrays in dToF-CIS.
  • * To design and characterize a global on-chip compensation loop for mitigating PVT effects.
  • * To demonstrate the effectiveness of the compensation loop in stabilizing TDC performance and enabling programmable time resolutions.

Main Methods:

  • * Detailed analysis of PVT variations' effects on TDC time bin stability.
  • * Design of an on-chip phase locked loop (PLL) featuring voltage-controlled ring-oscillators (VCROs).
  • * Implementation of a global compensation loop using a master VCRO to control slave VCROs, ensuring PVT invariance.

Main Results:

  • * The compensation loop effectively reduces TDC time bin spreading due to PVT variations.
  • * Temperature-induced spreading reduced from 20% to 2.4% (0-100 °C).
  • * Voltage supply variations (±10%) reduced spreading from 27% to 0.27%.
  • * Process parameter variation standard deviation decreased from 5.2 ps to 2 ps.

Conclusions:

  • * The proposed global compensation loop significantly enhances the stability and accuracy of dToF-CIS sensors.
  • * The system-level approach effectively mitigates performance degradation caused by PVT fluctuations.
  • * The compensation scheme enables precise 3D ranging and depth map imaging with programmable time resolutions.