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The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET.
Wei Li1, Hongxia Liu2, Shulong Wang3
1Key Laboratory for Wide Band Gap Semiconductor Materials and Devices of Education, School of Microelectronics, Xidian University, Xi'an, 710071, China.
Nanoscale Research Letters
|September 7, 2017
Summary
This study optimizes dual-gate tunneling field-effect transistor (DG-TFET) DRAM for improved performance. Optimized programming conditions significantly enhance retention time and reduce power consumption in capacitorless DRAM cells.
Area of Science:
- Semiconductor device physics
- Integrated circuit design
- Memory technology
Background:
- Traditional one transistor-one capacitor (1T-1C) dynamic random access memory (DRAM) suffers from large capacitor volume and high leakage current.
- Tunneling field-effect transistors (TFETs) offer low off-state current and high switching ratios, making them suitable for DRAM applications.
- Dual-gate TFET (DG-TFET) DRAM presents a capacitorless structure with enhanced retention time and reduced temperature dependence.
Purpose of the Study:
- To investigate and optimize the programming conditions for DG-TFET DRAM.
- To provide guidelines for enhancing the performance of TFET-based DRAM.
- To analyze the impact of programming on the writing and reading operations of DG-TFET DRAM.
Main Methods:
- Utilized the Silvaco Atlas simulation tool for detailed analysis.
- Investigated the band-to-band tunneling (BTBT) mechanisms governing write and read operations.
- Determined optimal gate voltages for hole storage and retention during the '1' state.
Main Results:
- Achieved a high current ratio of reading '1' to reading '0' (10^7) with optimized programming.
- Demonstrated a retention time (RT) exceeding 2 seconds.
- Showcased the sensitivity of TFET DRAM performance to programming conditions.
Conclusions:
- Optimized programming conditions are crucial for achieving superior performance in DG-TFET DRAM.
- The proposed optimization significantly improves retention time, reducing the need for frequent refreshing.
- Enhanced RT leads to lower dynamic power consumption in DRAM systems.
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