A 12-Gb/s Stacked Dual-Channel Interface for CMOS Image Sensor Systems

Area of Science:

• Electrical Engineering
• Computer Engineering
• Materials Science

Background:

• High-speed data transmission is critical for modern electronics.
• Reducing power consumption in transceivers is a key challenge.
• Existing architectures face limitations in managing signal integrity and power efficiency.

Purpose of the Study:

• To propose a novel dual-channel interface architecture for efficient high-speed data transmission.
• To reduce power consumption in the transmitter design.
• To ensure robust signal reception by managing common-mode variations and channel loss.

Main Methods:

• A dual-channel architecture separating high and low transition-density bit streams.
• Stacked drivers with charge-recycling for power reduction in the transmitter.
• Direct current (DC)-coupled receiver front-end for level variation management and loss compensation.
• A shared tracked oversampling clock and data recovery (CDR) for fast lock acquisition and low latency.

Main Results:

• Fabrication in 65-nm low-power complementary metal-oxide semiconductor (CMOS) technology.
• Achieved a 12-Gb/s data rate.
• Transmitter power consumption of 20.43 mW from a 1.2-V supply.

Conclusions:

• The proposed dual-channel interface architecture effectively supports high-speed data rates.
• The design demonstrates significant power savings through charge-recycling and stacked drivers.
• The integrated CDR and receiver front-end ensure reliable data recovery and signal integrity.