A Sub- μW/Ch Analog Front-End for ∆-Neural Recording With Spike-Driven Data Compression.

Area of Science:

• Neuroscience
• Biomedical Engineering
• Integrated Circuit Design

Background:

• Brain activity monitoring requires efficient neural recording systems.
• Existing systems face challenges with power consumption and data bandwidth.
• Need for low-power, high-resolution neural interfaces.

Purpose of the Study:

• To develop a fully implantable neural recording IC with improved power efficiency.
• To implement a spike-driven data compression scheme for neural data.
• To reduce power dissipation and data volume for brain monitoring.

Main Methods:

• Utilized a difference (∆) neural signal sampling to reduce analog-to-digital converter (ADC) requirements.
• Implemented analog memory for feature extraction (magnitude, frequency) of neural signals.
• Developed an energy-efficient successive approximation ADC that only converts detected spikes.
• Fabricated a 16-channel neural interface IC using a 0.18-μm CMOS process.

Main Results:

• Achieved precise spike detection in both in vitro and in vivo neural signal acquisition.
• The prototype chip consumed only 0.88 μW/channel at a 0.5-V supply.
• Demonstrated approximately 89% neural data compression.
• Enabled analog chain operation at a low 0.5-V supply.

Conclusions:

• The developed neural recording IC offers significant power and bandwidth savings.
• Spike-driven data compression effectively reduces data volume while preserving critical information.
• The system is suitable for power-constrained, long-term brain activity monitoring applications.