An Improved Update Rate CDR for Interference Robust Broadband Human Body Communication Receiver

Area of Science:

• Electrical Engineering
• Biomedical Engineering
• Signal Processing

Background:

• Broadband Human Body Communication (HBC) offers energy-efficient data transfer for body area networks by leveraging the human body's conductivity.
• Environmental interference significantly hinders the performance and reliability of HBC systems.
• Existing HBC receivers require robust Clock Data Recovery (CDR) loops to accurately sample data, especially in noisy environments.

Purpose of the Study:

• To address the challenge of environmental interference in broadband HBC systems.
• To propose and evaluate a novel, interference-tolerant Clock Data Recovery (CDR) architecture for integrating front-end HBC receivers.
• To enhance the robustness and performance of data sampling in broadband HBC.

Main Methods:

• Analysis of traditional Baud Rate CDR within an integrating front-end receiver framework.
• Development of a modified integrating CDR architecture featuring a higher update rate.
• Implementation and real-time validation of the proposed CDR on a Xilinx Spartan-3E FPGA board.

Main Results:

• The proposed CDR exhibits 2.5X greater clock-data frequency offset tolerance than traditional Baud Rate CDR.
• It demonstrates over 1.25X improved frequency offset tolerance in the presence of environmental interference.
• The architecture shows over 10% interference frequency offset tolerance relative to the integration clock.

Conclusions:

• The modified integrating CDR architecture significantly enhances interference robustness and frequency offset tolerance for broadband HBC.
• FPGA implementation confirms the real-time closed-loop functionality of the proposed CDR.
• This advancement is crucial for reliable and efficient operation of future body area network devices using HBC technology.