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Parasitic engineering for RRAM control.

P R Shrestha1,2, D M Nminibapiel2,3, D Veksler2

  • 1Theiss Research, La Jolla, CA, USA.

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|September 27, 2019
PubMed
Summary
This summary is machine-generated.

Minimizing current overshoot in filamentary resistive random-access memory (RRAM) is not always beneficial. Optimizing parasitic capacitance, rather than minimizing it, enhances filament stability and control in RRAM devices.

Keywords:
Current overshootFormingResistive random access memory (RRAM)Switching variability

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Area of Science:

  • Materials Science
  • Electrical Engineering
  • Device Physics

Background:

  • Current overshoot in filamentary resistive random-access memory (RRAM) is often seen as a source of variability.
  • Attempts to minimize this overshoot involve reducing parasitic capacitance in 1T-1R or 1R-1R structures.
  • This approach faces challenges in large-scale memory array designs.

Purpose of the Study:

  • To investigate the relationship between parasitic capacitance, current overshoot, and filament stability in RRAM.
  • To challenge the conventional approach of minimizing parasitic capacitance for improved device performance.
  • To propose an optimized parasitic capacitance strategy for enhanced filament control.

Main Methods:

  • Utilizing an energy-based understanding of filamentary forming in RRAM devices.
  • Analyzing the impact of varying parasitic capacitance levels on filament formation.
  • Comparing device behavior in optimized versus minimized capacitance configurations.

Main Results:

  • Contrary to common belief, minimizing parasitic capacitance can lead to insufficient current for stable filament formation.
  • An optimized parasitic capacitance is crucial for achieving reliable filamentary switching.
  • The study demonstrates that controlled parasitic capacitance enhances filament stability and device control.

Conclusions:

  • The conventional strategy of minimizing parasitic capacitance in RRAM is counterproductive for filament stability.
  • Parasitic capacitance should be optimized, not minimized, to ensure robust filament formation and control.
  • This finding offers a new perspective for designing high-performance and reliable RRAM arrays.