Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional...

Area of Science:

• Semiconductor device physics
• Nanotechnology
• Materials science

Background:

• Monolithic three-dimensional integrated circuits (3D-ICs) require advanced fabrication techniques for stacked devices.
• Achieving high performance and low power consumption in integrated circuits is crucial for mobile and neuromorphic applications.
• Existing gate-all-around (GAA) nanowire (NW) field-effect transistors (FETs) face challenges in controlling grain boundaries and thermal budgets.

Purpose of the Study:

• To introduce a novel single-grain GAA Si NW FET fabrication method.
• To investigate the process verification and electrical characteristics of these FETs.
• To demonstrate the potential for ultrahigh-density, sequentially stackable 3D-ICs.

Main Methods:

• Utilized location-controlled-grain technique for precise nanowire fabrication.
• Employed low-thermal budget processes: green nanosecond laser crystallization, far-infrared laser annealing, and hybrid laser-assisted salicidation (<400 °C substrate temperature).
• Fabricated and characterized single-grain GAA Si NW FETs within controlled Si grains.

Main Results:

• Achieved a steeper subthreshold swing (S.S.) of ~65 mV/dec.
• Obtained higher driving currents: 327 µA/µm (n-type) and 297 µA/µm (p-type) at Vth ± 0.8 V.
• Demonstrated superior I_on/I_off ratio (>10⁵ at |V_d| = 1 V) and narrower electrical property distribution compared to omega(Ω)-gate FETs.
• Exhibited reduced sensitivity to V_th roll-off and S.S. degradation.

Conclusions:

• The single-grain GAA Si NW FETs offer enhanced electrical performance and reliability.
• The low-thermal budget fabrication is compatible with monolithic 3D-IC integration.
• This technology paves the way for next-generation ultrahigh-density, high-performance, low-power integrated circuits.