A 2.3-ps RMS Resolution Time-to-Digital Converter Implemented in a Low-Cost Cyclone V FPGA.

Area of Science:

• Digital electronics
• Integrated circuit design
• Signal processing

Background:

• Time-to-digital converters (TDCs) are crucial for precise timing measurements.
• Existing high-resolution TDCs often rely on expensive FPGAs with fine delay lines.
• Low-cost FPGAs present challenges in achieving high timing resolution due to limited delay line uniformity.

Purpose of the Study:

• To introduce a novel nonuniform multiphase (NUMP) method for constructing high-resolution TDCs.
• To demonstrate the feasibility of implementing NUMP TDCs in low-cost field-programmable gate array (FPGA) devices.
• To evaluate the timing resolution performance of the NUMP method.

Main Methods:

• The NUMP method utilizes a system clock passed through delay elements to create multiple phase-shifted clocks.
• It sorts clock edge phases and latches states upon a hit signal arrival.
• The method leverages general FPGA delay sources, not limited to fine carry chains, for clock randomization.

Main Results:

• The NUMP method achieves timing resolutions not constrained by the uniformity or minimum value of delay lines.
• Implemented NUMP TDCs in a low-cost FPGA (Altera Cyclone V) demonstrated excellent performance.
• Measured root mean square (rms) timing resolutions of 2.3 ps and 5.2 ps for internal and external pulses (<1 ns), and 14.1 ps at 517 ns.

Conclusions:

• The NUMP method offers a viable approach for high-resolution TDC implementation in cost-effective FPGAs.
• It overcomes limitations of traditional methods by not requiring specialized fine delay lines.
• The NUMP method is suitable for applications needing numerous high-performance TDC channels within budget constraints.