Cross-Detection for Bubble-free Thermometer Codes and Dual-Side Monitoring for FPGA-Based High-Accuracy and...

Area of Science:

• Digital electronics
• Instrumentation
• FPGA-based systems

Background:

• Time-to-digital converters (TDCs) are crucial for high-resolution timing applications.
• Conventional TDCs face limitations in accuracy due to timing inaccuracies and environmental variations.
• Existing architectures often require significant resources and exhibit non-linearities.

Purpose of the Study:

• To develop a novel FPGA-based TDC architecture for enhanced timing resolution and stability.
• To introduce innovative cross-detection (CD) and dual-side monitoring (DSM) techniques to mitigate TDC inaccuracies.
• To provide a resource-efficient TDC design suitable for demanding timing applications.

Main Methods:

• Implemented a novel TDC architecture on a Xilinx Virtex-7 FPGA.
• Utilized a cross-detection (CD) method to minimize bubbles in thermometer codes, reducing average bin size.
• Employed dual-side monitoring (DSM) to capture both start-of-propagation (SOP) and end-of-propagation (EOP) codes for calibration.

Main Results:

• Achieved an average bin size of 5.6 ps and RMS bin distribution of 6.4 ps.
• Demonstrated superior linearity with DNL range of [-0.9, 2.7] LSB and INL range of [-2.1, 8.1] LSB.
• Successfully measured ultra-high timing resolution (83 ± 3.5 ps FWHM) of photomultiplier tubes, comparable to high-precision oscilloscopes.

Conclusions:

• The proposed CD-DSM TDC architecture offers superior performance compared to state-of-the-art TDCs.
• The novel techniques significantly enhance timing resolution, linearity, and stability.
• This FPGA-based TDC is a viable solution for high-resolution timing applications requiring precision and efficiency.