Cross-Detection for Bubble-free Thermometer Codes and Dual-Side Monitoring for FPGA-Based High-Accuracy and...

This study presents a novel field-programmable gate array (FPGA)-based time-to-digital converter (TDC) architecture designed for high-resolution timing applications, incorporating two innovative techniques. First, a cross-detection (CD) method modifies the sampling pattern to minimize bubbles in thermometer codes, which are a primary source of inaccuracy in TDC timing measurements. By eliminating these bubbles, the method reduces the average bin size by half. Second, dual-side monitoring (DSM) simultaneously captures both end-of-propagation (EOP) and start-of-propagation (SOP) thermometer codes. Unlike conventional TDCs that rely solely on SOP, DSM leverages EOP to calibrate SOP, thereby enhancing time resolution and improving stability under temperature and location variations. The proposed DSM scheme requires only two additional CARRY4s to capture EOP, offering a resource-efficient alternative to conventional TDC designs. The proposed CD-DSM TDC was implemented on a Xilinx Virtex-7 (XC7VX485T-2FFG1761C) FPGA, achieving an average bin size of 5.6 ps and a root mean square bin distribution of 6.4 ps. It demonstrates superior linearity, with a differential non-linearity (DNL) range of [-0.9, 2.7] least significant bits (LSB) and an integral non-linearity (INL) range of [-2.1, 8.1] LSB. The ultra-high timing resolution of two Cerenkov radiator integrated microchannel plate photomultiplier tubes was successfully measured using two identical CD-DSM TDCs. The full width at half maximum of the measured coincidence timing histogram was 83 ± 3.5 ps, closely matching the 85 ± 4.8 ps timing resolution obtained using a high-precision oscilloscope. A comparison with state-of-the-art TDCs highlights the superior performance of the CD-DSM TDC.