A 6-Transistor Ultra-Low Power CMOS Voltage Reference with 0.02%/V Line Sensitivity

Area of Science:

• Integrated Circuit Design
• Solid-State Electronics
• Low-Power Electronics

Background:

• Accurate and stable voltage references are crucial for modern electronic systems.
• Existing ultra-low power (ULP) voltage references often struggle with line sensitivity and temperature variations.
• Advanced CMOS technologies require novel approaches for efficient power management.

Purpose of the Study:

• To present a novel technique for designing ultra-low power (ULP) CMOS voltage references.
• To achieve exceptionally low line sensitivity and high temperature stability.
• To validate the technique in sub-100 nm CMOS technologies.

Main Methods:

• Utilized a 6-transistor (6T) structure for the voltage reference design.
• Implemented the technique in a 65-nm CMOS process.
• Characterized performance metrics including line sensitivity, temperature coefficient, and power consumption.

Main Results:

• The 65-nm CMOS implementation occupies a small area of 840 µm².
• Achieved an ultra-low power consumption of 28.6 pA from a 0.5 V supply.
• Demonstrated an average line sensitivity of 0.02 %/V and a temperature coefficient of 99.2 ppm/°C.

Conclusions:

• The proposed 6T technique enables ULP CMOS voltage references with superior performance.
• The design offers a significant improvement in line sensitivity (10x) compared to prior work.
• This approach is well-suited for advanced sub-100 nm CMOS technologies demanding low power and high stability.