Reconfigurable Architectures with High-Frequency Noise Suppression for Wearable ECG Devices.

Area of Science:

• Biomedical Engineering
• Digital Signal Processing
• Embedded Systems

Background:

• Low-cost electronics enable widespread use of remote health monitoring devices.
• ECG signal acquisition is susceptible to high-frequency noise, power-line interference, and baseline drift, hindering accurate diagnostics.
• Traditional FIR filters for noise reduction increase critical path delay with filter length.

Purpose of the Study:

• To investigate efficient methods for reducing high-frequency noise in ECG signals.
• To improve the clock speed of digital filters used in ECG signal processing.
• To compare the performance of conventional and proposed moving average filters on an FPGA.

Main Methods:

• Implementation of simple moving average (MA) filters using pipelining and look-ahead transformation techniques.
• Design and synthesis of conventional and recursive pipelined 8-tap MA filters.
• Hardware implementation on an Altera Cyclone IV FPGA using Quartus II software.

Main Results:

• The recursive pipelined 8-tap MA filter with the look-ahead approach achieved the highest clock speed at 685.48 MHz.
• Performance metrics including logic element usage, clock speed, and power consumption were evaluated.
• The proposed filter design demonstrated significant improvements in clock speed compared to conventional methods.

Conclusions:

• Pipelining and look-ahead techniques effectively increase the clock speed of MA filters for ECG signal processing.
• The recursive pipelined 8-tap MA filter with look-ahead is a highly efficient design for noise reduction in remote health monitoring applications.
• Optimized digital filter design is crucial for enhancing the diagnostic accuracy and reliability of wearable ECG devices.