One dimensional MOSFETs for sub-5 nm high-performance applications: a case of Sb₂Se₃ nanowires

Low-dimensional materials have been proposed as alternatives to silicon-based field-effect transistor (FET) channel materials in order to overcome the scaling limitation. In the present research, gate-all-around (GAA) Sb₂Se₃ nanowire FETs were simulated using the ab initio quantum transport method. The gate-length (L_g, L_g = 5 nm) GAA Sb₂Se₃ FETs with an underlap (UL, UL = 2, 3 nm) could satisfy the on-state current (I_on) and delay time (τ) of the 2028 requirements for high performance (HP) applications of the International Technology Roadmap for Semiconductors (ITRS) 2013. It is interesting that the L_g = 3 nm GAA Sb₂Se₃ FETs with a UL = 3 nm can meet the I_on, power dissipation (PDP), and τ of the 2028 requirements of ITRS 2013 for HP applications. Therefore, GAA Sb₂Se₃ FETs can be a potential candidate scaling Moore's law downward to 3 nm.