Sub-5 nm Gate-Length Monolayer Selenene Transistors

Area of Science:

• Materials Science
• Condensed Matter Physics
• Nanotechnology

Background:

• Silicon field-effect transistors (FETs) face scaling limitations.
• Two-dimensional (2D) semiconductors offer alternative channel materials.
• Air-stable 2D selenium nanosheet FETs have been experimentally demonstrated.

Purpose of the Study:

• To investigate the potential of sub-5 nm gate-length double-gate monolayer (ML) selenene FETs.
• To assess ML selenene as a candidate for future high-performance electronic devices.
• To evaluate performance metrics against established industry standards.

Main Methods:

• Ab initio quantum transport simulations were employed.
• Focus on double-gate monolayer (ML) selenene field-effect transistors (FETs).
• Consideration of negative-capacitance technology and underlap effects.

Main Results:

• Simulations predict 3 nm gate-length p-type ML selenene FETs can meet 2013 ITRS standards.
• Performance was analyzed for both armchair and zigzag crystallographic directions.
• The 2028 technology horizon was used as a benchmark.

Conclusions:

• Monolayer selenene demonstrates potential as a channel material for advanced FETs.
• ML selenene FETs could enable scaling of Moore's Law down to 3 nm gate lengths.
• This research highlights selenene's viability for next-generation semiconductor technology.