Development and Analysis of a Three-Fin Trigate Q-FinFET for a 3 nm Technology Node with a Strained-Silicon Channel...

Area of Science:

• Semiconductor device physics
• Nanoelectronics
• Materials science

Background:

• Multi-gate field-effect transistors (FETs) face short-channel effects (SCEs) below 14 nm, hindering nanoFET scaling and integrated circuit (IC) technology progress.
• Existing FinFETs show performance degradation due to SCEs and fringing capacitances, impacting semiconductor industry advancements.
• Current research struggles to meet the International Roadmap for Devices and Systems (IRDS) requirements for advanced ICs.

Purpose of the Study:

• To develop novel three-fin trigate (TG) quantum (Q)-FinFETs utilizing a tri-layered strained-silicon channel.
• To enhance ON currents, manage leakage currents, and improve SCEs for next-generation IC technologies.
• To enable continued progress in semiconductor industries by addressing limitations of current nanoFETs.

Main Methods:

• Deployment of three-fin TG quantum (Q)-FinFETs at 10 nm and 8 nm channel lengths.
• Analytical calculation of threshold voltage for design validation.
• Exploration and analysis of electrical parameters and quantum effects in comparison to existing devices and IRDS standards.

Main Results:

• Demonstrated significant increase in drive currents using three fins with identical dimensions (8 nm gate length).
• Achieved augmented performance compared to the IRDS 2022 3 nm technology node device.
• Maintained short-channel effects within acceptable limits in the proposed devices.

Conclusions:

• The developed three-fin Q-FinFET with a tri-layered strained-silicon channel is a viable technique for consolidating device performance.
• This approach enables future-generation devices for faster switching operations in the sub-nanometer regime.
• The study provides a pathway for overcoming scaling limitations and advancing IC technology.