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Enhanced Drive Current in 10 nm Channel Length Gate-All-Around Field-Effect Transistor Using Ultrathin Strained
Potaraju Yugender1, Rudra Sankar Dhar1, Swagat Nanda1
1Department of Electronics and Communication Engineering, National Institute of Technology Mizoram, Aizawl 796 012, Mizoram, India.
Micromachines
|January 8, 2025
Summary
A novel 10 nm Gate-All-Around Field-Effect Transistor (GAAFET) using strained silicon channels significantly enhances device performance. This design overcomes short channel effects, outperforming current specifications for future semiconductor applications.
Area of Science:
- Semiconductor Device Physics
- Materials Science
- Nanoelectronics
Background:
- Continuous scaling of MOSFETs faces limitations due to short channel effects (SCEs) beyond 22 nm technology.
- Strained silicon technology offers a viable solution to enhance drain current and mitigate SCEs in advanced nanodevices.
- Multi-gate architectures like FinFETs show promise but still contend with scaling challenges.
Purpose of the Study:
- To develop and analyze a novel 10 nm Gate-All-Around Field-Effect Transistor (GAAFET) incorporating a strained silicon channel.
- To investigate the impact of a strained silicon-germanium layer sandwiched between strained silicon layers on device performance.
- To compare the electrical characteristics of the proposed 10 nm GAAFET with existing 22 nm GAAFETs, FinFETs, and International Roadmap for Devices and Systems (IRDS) 2022 specifications.
Main Methods:
- Fabrication of a 10 nm gate length GAAFET with a unique strained silicon channel structure.
- Incorporation of strain engineering by using a strained silicon-germanium layer between two strained silicon layers.
- Comprehensive electrical characterization including on-current, off-current, threshold voltage (VTH), subthreshold slope, and DIBL.
Main Results:
- The 10 nm strained silicon GAAFET demonstrates superior electrical properties compared to the 22 nm version and the existing SOI FinFET.
- The proposed GAAFET design exhibits significantly improved on/off current ratios and reduced short channel effects.
- Performance metrics of the developed 10 nm GAAFET exceed the IRDS 2022 specifications, indicating enhanced device functionality.
Conclusions:
- The novel 10 nm strained silicon GAAFET architecture effectively suppresses short channel effects.
- This advanced GAAFET design offers a promising pathway for achieving higher performance in future nanoscale semiconductor devices.
- The integration of strain engineering in GAAFETs is crucial for pushing the boundaries of device scaling and performance.
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