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Phase/Interfacial-Engineered Two-Dimensional-Layered WSe2 Films by a Plasma-Assisted Selenization Process: Modulation

Mayur Chaudhary1,2,3,4,5, Yu-Chuan Shih1,3,4,5, Shin-Yi Tang1,3,4,5,6

  • 1Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan.

ACS Applied Materials & Interfaces
|July 10, 2023
PubMed
Summary

Researchers engineered a novel 2D-layered WSe2/WO3 heterolayer for improved resistive switching devices. This phase and interfacial engineering enhances device uniformity, multilevel characteristics, and retention times for advanced electronics.

Keywords:
2D layered-WSe2/WO3conducting filamentinterfacial engineeringplasma-assisted chemical vapor reactionthe functional layer

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Area of Science:

  • Materials Science and Engineering
  • Nanotechnology
  • Solid-State Electronics

Background:

  • Resistive switching (RS) devices are crucial for non-volatile memory applications.
  • Achieving stable and efficient RS characteristics requires precise control over material interfaces and phases.
  • Existing materials often face challenges with uniformity, multilevel storage, and retention.

Purpose of the Study:

  • To develop a novel 2D-layered WSe2/WO3 heterolayer structure for enhanced resistive switching performance.
  • To investigate the effects of phase and interfacial engineering on device characteristics.
  • To optimize the WSe2/WO3 ratio for improved uniformity, multilevel capabilities, and retention.

Main Methods:

  • Fabrication of a 2D-layered WSe2/WO3 heterolayer using plasma-assisted selenization of a WO3 layer.
  • Integration of the heterolayer with an Al2O3 resistive switching layer and Pt/W electrodes.
  • Systematic tuning of WSe2/WO3 ratios and investigation of 1T/2H WSe2 phase effects on electrical properties.

Main Results:

  • The Pt/Al2O3/(2D-layered WSe2/WO3)/W device demonstrated significantly improved performance over pristine structures.
  • Key improvements include reduced SET/RESET voltage variability (-20/20)%, excellent multilevel characteristics, high on/off ratios (104-105), and long retention times (∼105 s).
  • Optimizing the WSe2/WO3 ratio to 45/55% and utilizing the metallic 1T phase of WSe2 were critical for superior performance.

Conclusions:

  • Phase and interfacial engineering of WSe2/WO3 heterolayers offers a promising route to high-performance resistive switching devices.
  • The low-temperature plasma-assisted selenization process is compatible with 3D integration and enables large-area thickness control.
  • This approach provides a pathway for developing more robust and efficient non-volatile memory technologies.