The Design of a Dynamic Configurable Packet Parser Based on FPGA.

Area of Science:

• Computer Engineering
• Network Architecture
• Hardware Acceleration

Background:

• Traditional fixed-type protocol parsers struggle to meet the dynamic demands of modern programmable networks.
• Existing solutions often face limitations in latency and configurability, hindering network flexibility.

Purpose of the Study:

• To propose a dynamic and configurable low-latency parser implemented on Field-Programmable Gate Arrays (FPGAs).
• To enhance network adaptability and efficiency by addressing the limitations of conventional protocol parsers.

Main Methods:

• Designed an FPGA architecture featuring three protocol analysis modules and TCAM-SRAM for efficient data processing.
• Optimized state machine and parallel extraction matching to reduce latency.
• Introduced chain mapping and container concepts for flexible rule formulation and enhanced parser extensibility, with dynamic configuration via Software-Defined Networking (SDN).

Main Results:

• Achieved a throughput exceeding 80 Gbps on Xilinx Ultrascale+ FPGAs.
• Demonstrated a maximum latency of only 36 nanoseconds for Layer 4 (L4) protocol parsing.
• Verified and simulated the design using a cocotb-based framework.

Conclusions:

• The proposed dynamic FPGA parser offers a low-latency, high-throughput solution for programmable networks.
• The architecture provides flexible adaptation to diverse network scenarios through dynamic SDN control.
• This approach significantly improves upon the limitations of traditional fixed-type protocol parsers.