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Updated: Jun 29, 2025

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Published on: April 13, 2016
Modern Trends in Microelectronics Packaging Reliability Testing
Emmanuel Bender1,2, Joseph B Bernstein2, Duane S Boning1
1Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA 02142, USA.
Abstract:
In this review, recent trends in microelectronics packaging reliability are summarized. We review the technology from early packaging concepts, including wire bond and BGA, to advanced techniques used in HI schemes such as 3D stacking, interposers, fan-out packaging, and more recently developed silicon interconnect fabric integration. This review includes approaches for both design modification studies and packaged device validation. Methods are explored for compatibility in new complex packaging assemblies. Suggestions are proposed for optimizations of the testing practices to account for the challenges anticipated in upcoming HI packaging schemes.
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