Impact of Hydrogen Voiding in Chip-to-Chip Electroless All-Copper Interconnections

Three-dimensional (3D) integration has become a leading approach in chip packaging. The interconnection density and reliability of micro-bumps in chip stacking are often threatened by high bonding temperatures. The method of building chip-to-chip interconnections by electroless deposition of metal has its distinct merit, while the interfacial defect issue, especially that related to voiding during the merging of opposite sides, remains largely unsolved. In this study, to trace the influencing factors in the voiding, the growth characteristics of the electroless all-copper interconnections were examined by carrying out deposition experiments in a microfluidic channel device. The results show that when the gap between the opposite copper bumps to be electrolessly merged is as low as 10 μm, significant voids appear at the inflow side and the top of the copper bumps because the hydrogen cannot be expelled in time. A finite-element flow model of the plating solution between the chips was established, which showed that the flow rate of the plating solution around the copper bumps was much higher than in the merging gap, causing an uneven supply of reactants. Based on these findings, we proposed two potential solutions, one is to improve the flow mode of the plating solution, and the other is to add the reaction inhibitor, 2,2'-bipyridine. Finally, the combination of these two approaches successfully achieved an improved merging quality of the copper joints.