An Efficient SM9 Aggregate Signature Scheme for IoV Based on FPGA.

Area of Science:

• Cryptography
• Computer Engineering
• Network Security

Background:

• The Internet of Vehicles (IoV) requires secure and efficient signature verification due to rapid development.
• Existing schemes may not adequately address the demands of diverse network environments.
• The need for robust cryptographic solutions in vehicular networks is paramount.

Purpose of the Study:

• To propose an efficient SM9 aggregate signature scheme implemented on Field-Programmable Gate Array (FPGA).
• To develop both fault-tolerant and non-fault-tolerant aggregate signature modes for various network conditions.
• To enhance signature verification speed and efficiency in IoV environments.

Main Methods:

• Implementation of an SM9 aggregate signature scheme on FPGA.
• Design of fault-tolerant and non-fault-tolerant aggregate signature modes.
• Development of an efficient parallel point multiplication architecture using FPGA capabilities, optimized with Montgomery multiplication and Barrett reduction algorithms.
• Security proofs based on the K-ary Computational Additive Diffie-Hellman (K-CAA) problem.

Main Results:

• Achieved a point multiplication speed of 70,776 times per second.
• Non-fault-tolerant mode reduced verification time by up to 97.1% compared to other schemes in error-free conditions.
• Fault-tolerant mode reduced verification time by up to 77.2% compared to other schemes.
• The proposed fault-tolerant scheme's verification time is only 28.9% of other fault-tolerant schemes.
• Non-fault-tolerant mode verification time reduced by at least 39.1% compared to other schemes.

Conclusions:

• The proposed FPGA-based SM9 aggregate signature scheme offers significant improvements in verification efficiency.
• The scheme demonstrates substantial advantages in both error-free and fault-tolerant scenarios for IoV.
• The optimized parallel architecture effectively addresses the computational demands of vehicular network security.