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Hafnia-Based Ferroelectric Transistor with Poly-Si Gates for Gate-First Three-Dimensional NAND Structures.

Ik-Jyae Kim1, Jiwoung Choi1, Jang-Sik Lee1

  • 1Department of Materials Science and Engineering, Pohang University of Science and Technology (POSTECH), Pohang 37673, Republic of Korea.

ACS Applied Materials & Interfaces
|November 20, 2024
PubMed
Summary
This summary is machine-generated.

Polycrystalline silicon (poly-Si) can replace conventional materials in hafnia-based ferroelectric transistors for 3D NAND memory. This simplifies fabrication by enabling a gate-first process, reducing manufacturing steps.

Keywords:
3D structureferroelectric materialferroelectric memorygate electrodepoly silicon

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Area of Science:

  • Materials Science
  • Electrical Engineering
  • Semiconductor Device Physics

Background:

  • Hafnia-based ferroelectric transistors are key for advanced memory, including 3D NAND.
  • Conventional 3D NAND uses TiN or W gates, requiring complex gate-last processing and replacement steps.

Purpose of the Study:

  • To investigate polycrystalline silicon (poly-Si) as a gate material for hafnia-based ferroelectric transistors in 3D NAND.
  • To evaluate the feasibility of a simplified fabrication process using poly-Si gates.

Main Methods:

  • Fabrication of hafnia-based ferroelectric transistors utilizing poly-Si as the gate electrode.
  • Integration of these transistors into a 3D NAND architecture.
  • Comparison of the proposed gate-first process with conventional gate-last methods.

Main Results:

  • Demonstrated successful use of poly-Si as a gate material for hafnia-based ferroelectric transistors.
  • Showcased a simplified gate-first fabrication process for 3D ferroelectric NAND devices.
  • Eliminated the need for a gate replacement step, common in gate-last processes.

Conclusions:

  • Poly-Si is a viable gate material for hafnia-based ferroelectric transistors in 3D NAND.
  • The use of poly-Si enables a more efficient gate-first fabrication process for 3D ferroelectric NAND.
  • This approach offers a simpler and potentially more cost-effective manufacturing route for next-generation memory devices.