Reducing Avalanche Build-Up Time by Integrating a Single-Photon Avalanche Diode with a BiCMOS Gating Circuit.

Area of Science:

• Photonics
• Integrated Circuits
• Semiconductor Devices

Background:

• Single-photon avalanche diodes (SPADs) are crucial for sensitive light detection.
• Parasitic capacitance in SPAD circuits can limit performance, particularly avalanche build-up time.
• Traditional SPAD designs often involve off-chip gating circuits, introducing bondpad capacitance.

Purpose of the Study:

• To investigate the impact of integrating a SPAD with a BiCMOS gating circuit on a single chip.
• To quantify the reduction in avalanche build-up time achieved through this integration.
• To compare the performance of an integrated BiCMOS gating circuit with a standard CMOS gating circuit.

Main Methods:

• Fabrication of an integrated SPAD and BiCMOS gating circuit using a 0.35 μm CMOS process extended with an NPN transistor module.
• Measurement of gating voltage transients using an integrated mini-pad and a picoprobe.
• Comparison of avalanche build-up times between the integrated BiCMOS SPAD and an off-chip wire-bonded SPAD.

Main Results:

• On-chip integration eliminated bondpad capacitance, a significant contributor to parasitic capacitance.
• The integrated BiCMOS gating circuit reduced SPAD avalanche build-up time to 1.6 ns.
• This represents approximately a twofold improvement compared to ~3 ns for an off-chip wire-bonded SPAD.

Conclusions:

• Chip-level integration of SPADs and BiCMOS gating circuits effectively minimizes parasitic capacitance.
• This approach substantially reduces avalanche build-up time, enhancing SPAD operational speed.
• The developed BiCMOS technology enables faster and more efficient single-photon detection systems.