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The Design of a Low-Noise CMOS Image Sensor Using a Hybrid Single-Slope Analog-to-Digital Converter
Hyun Seon Choo1, Da-Hyeon Youn1, Hyunggyu Choi1
1Department of System Semiconductor, Dongguk University, Seoul 04620, Republic of Korea.
Sensors (Basel, Switzerland)
|January 8, 2025
Summary
This study introduces a novel 10/11-bit hybrid analog-to-digital converter (ADC) for low-noise complementary metal-oxide semiconductor (CMOS) image sensors (CIS). The hybrid ADC enhances low-light performance and reduces power consumption in high-light conditions.
Area of Science:
- * Solid-state device physics
- * Integrated circuit design
- * Image sensor technology
Background:
- * Complementary metal-oxide semiconductor (CMOS) image sensors (CIS) are crucial for digital imaging.
- * Achieving high resolution and low noise simultaneously, especially under varying light conditions, remains a challenge.
- * Existing analog-to-digital converters (ADCs) often face trade-offs between noise performance, resolution, and power consumption.
Purpose of the Study:
- * To develop and characterize a novel 10/11-bit hybrid single-slope analog-to-digital converter (SS-ADC) for CIS applications.
- * To improve noise performance in low-light conditions while maintaining high resolution.
- * To reduce power consumption in high-light conditions without compromising image quality.
Main Methods:
- * Implementation of a hybrid SS-ADC architecture combining 11-bit resolution for low-light and 10-bit for high-light.
- * Utilizing a digital-correlated double sampling method with a double data rate structure for enhanced low-light noise reduction.
- * Fabrication of the CIS using a 110 nm 1-poly 4-metal CIS process.
Main Results:
- * The proposed hybrid SS-ADC achieved an 8% reduction in dark random noise in low-light conditions compared to existing 10-bit ADCs.
- * In high-light conditions, using 10-bit resolution resulted in an approximate 31% decrease in dynamic power consumption compared to an 11-bit ADC.
- * Demonstrated linear in-out characteristics and maintained comparable noise performance to an 11-bit SS-ADC under low-light conditions.
Conclusions:
- * The developed 10/11-bit hybrid SS-ADC effectively balances noise performance and power consumption for CMOS image sensors.
- * This hybrid approach offers a significant improvement for CIS applications operating under diverse lighting environments.
- * The fabricated sensor demonstrates the viability of the proposed hybrid ADC design for next-generation imaging systems.
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