Study of High Performance Nanoscale Channel Length Vertical Transistors with a Self-Aligned Blocking Layer.

Area of Science:

• Semiconductor physics
• Materials science
• Nanotechnology

Background:

• Vertically stacked transistors offer simple fabrication and high conductivity due to short channel lengths.
• Existing designs face challenges with gate field blocking and high off-state leakage current.
• These limitations hinder their adoption as a major transistor architecture.

Purpose of the Study:

• To address gate field blocking and leakage current in vertical transistors.
• To propose a fabrication method for high-performance nanoscale vertical transistors.
• To investigate the use of graphene electrodes for improved device characteristics.

Main Methods:

• Introduced a blocking layer (BL) with embedded holes and a source electrode with embedded holes.
• Developed a self-aligning lithography method with a built-in mask for precise alignment.
• Replaced metal electrodes with Fermi level-tunable graphene to mitigate short-channel effects.

Main Results:

• Achieved a transistor output of 28 mA/cm² and an on-off ratio exceeding 10⁶ at 1 mV VDS.
• The novel design demonstrated robust electrical properties, stability under bias stress, and light insensitivity.
• Graphene electrodes maintained low off-current (<10 pA) and an on-off ratio around 10⁷ at 3 V VDS.

Conclusions:

• The proposed vertical transistor design with embedded holes and graphene electrodes overcomes key limitations of previous designs.
• The self-aligning lithography method enables efficient, large-area fabrication of high-performance nanoscale transistors.
• This advanced vertical transistor architecture shows significant potential for diverse electronic applications.