Sub-Nanometer Equivalent Oxide Thickness and Threshold Voltage Control Enabled by Silicon Seed Layer on Monolayer...

Area of Science:

• Materials Science
• Nanotechnology
• Semiconductor Physics

Background:

• Two-dimensional (2D) semiconductors offer potential for advanced electronics but require ultrathin gate insulators.
• Atomic Layer Deposition (ALD) of these insulators on 2D materials is challenging due to surface sensitivity.
• Achieving high-quality interfaces is crucial for low-power transistor performance.

Purpose of the Study:

• To develop an effective surface preparation method for ALD of gate insulators on monolayer MoS₂.
• To achieve sub-1 nm equivalent oxide thickness (EOT) for HfO₂ gate dielectrics on MoS₂.
• To enable the fabrication of high-performance, low-power transistors using 2D semiconductors.

Main Methods:

• Investigated six seed layer candidates (Si, Ge, Hf, La, Gd, Al₂O₃) for surface preparation.
• Utilized Atomic Layer Deposition (ALD) to deposit HfO₂ gate dielectric on monolayer MoS₂.
• Fabricated and characterized monolayer MoS₂ transistors with HfO₂ top-gate dielectric.

Main Results:

• Si and Ge seed layers were found to be non-damaging to MoS₂.
• A Si seed layer resulted in a superior, low-hysteresis interface compared to Ge.
• Achieved sub-1 nm EOT (≈ 0.9 nm) with low leakage (<0.6 μA/cm²) and a subthreshold swing of ∼80 mV/dec.
• Demonstrated control over threshold voltage via interfacial layer thickness, enabling normally-off transistors.

Conclusions:

• A simple Si seed layer facilitates high-quality ALD of HfO₂ on monolayer MoS₂.
• This method enables the fabrication of advanced low-power transistors with excellent electrical characteristics.
• The approach is compatible with standard nanofabrication facilities, promoting wider adoption.