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Automatic Extraction and Compensation of P-Bit Device Variations in Large Array Utilizing Boltzmann Machine Training.

Bolin Zhang1,2, Yu Liu1,3, Tianqi Gao1,2

  • 1National Key Laboratory of Spintronics, Hangzhou International Innovation Institute, Beihang University, Hangzhou 311115, China.

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|March 17, 2025
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Summary

This study introduces a new algorithm to precisely extract variations in Probabilistic Bit (P-Bit) devices. This enables accurate Ising computation on large P-Bit arrays, overcoming hardware limitations for complex problems.

Keywords:
Boltzmann machine trainingIsing computationinteger factorizationmagnetic tunneling junctionspintronicstraveling salesman problem

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Area of Science:

  • Quantum Computing Hardware
  • Computational Physics
  • Materials Science

Background:

  • Probabilistic Bit (P-Bit) devices are fundamental for Ising computation.
  • Intrinsic variations in P-Bit devices limit the scalability of Ising computation arrays.
  • Existing methods struggle with accurate, simultaneous extraction of P-Bit variation parameters (α and ΔV).

Purpose of the Study:

  • To propose a behavioral model for P-Bit variations (α and ΔV).
  • To introduce a weight compensation method to mitigate P-Bit variations.
  • To develop a novel algorithm for accurate and scalable extraction of P-Bit variations.

Main Methods:

  • Developed a behavioral model attributing P-Bit variations to parameters α and ΔV.
  • Introduced a weight compensation technique by rederiving the weight matrix.
  • Presented an automatic variation extraction algorithm based on Boltzmann machine learning and a 3D ferromagnetic Ising Hamiltonian model.

Main Results:

  • Successfully extracted α and ΔV variations from large P-Bit arrays.
  • Demonstrated the Automatic Extraction and Compensation algorithm's effectiveness on 16-city TSP and 21-bit integer factorization.
  • Validated the algorithm's accuracy, transferability, and scalability on P-Bit arrays with inherent variations.

Conclusions:

  • The proposed algorithm enables precise and scalable variation extraction in large P-Bit arrays.
  • Weight compensation effectively mitigates P-Bit variations, allowing computation with ideal P-Bits.
  • This approach significantly enhances the practical applicability of Ising computation by overcoming hardware limitations.