Electrolyte-Gated Transistor Array (20 × 20) with Low-Programming Interference Based on Coplanar Gate Structure for...

Area of Science:

• Materials Science and Engineering
• Electrical Engineering
• Computer Science

Background:

• Compute-in-memory (CIM) offers a solution to data transmission bottlenecks in computing.
• Traditional two-terminal devices in CIM face challenges like leakage current and high power consumption.
• Large-scale demonstrations of three-terminal electrolyte-gated transistors (EGTs) for CIM are limited due to fabrication complexities.

Purpose of the Study:

• To design and demonstrate a large-scale EGT array for efficient CIM applications.
• To overcome the limitations of existing CIM technologies using transistor-based arrays.
• To showcase the potential of EGTs in building integrated synaptic arrays for advanced computing.

Main Methods:

• Fabrication of a 20x20 EGT array using indium-gallium-zinc-oxide and a doped polyacrylonitrile electrolyte.
• Characterization of individual EGTs as synapses, evaluating conductance range, energy consumption, repeatability, and update linearity.
• Implementation of unsupervised learning using a winner-takes-all neural network with 54 EGTs.

Main Results:

• The EGT array demonstrated precise device programming with minimal signal interference between adjacent devices.
• Individual EGTs exhibited low energy consumption (6.984 fJ) for read-write operations and quasilinear update characteristics.
• The neural network achieved 100% accuracy in letter classification after 50 training iterations.

Conclusions:

• The developed EGT array shows significant promise for large-scale integration in synaptic circuits.
• This work highlights the potential of EGTs to enable efficient and high-performance computing architectures.
• The demonstrated unsupervised learning capability underscores the viability of EGTs for neuromorphic computing applications.