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Updated: May 13, 2025

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics
Published on: August 28, 2018
Top-Gated P-MOSFET with CVD-Grown WSe2 Channels via Self-Aligned WO Conversion for Spacer Doping.
Meng-Zhan Li1,2, Terry Y T Hung2, Wei-Sheng Yun2
1Department of Physics, National Taiwan University, Taipei 10617, Taiwan.
Tungsten oxide (WO) conversion effectively dopes tungsten diselenide (WSe2) field-effect transistors (FETs). This method enhances on-current and mobility in devices made from CVD-grown films, applicable to future logic circuits.
Area of Science:
- Materials Science
- Nanotechnology
- Semiconductor Device Physics
Background:
- Tungsten diselenide (WSe2) field-effect transistors (FETs) are crucial for next-generation electronics.
- Previous doping strategies often relied on exfoliated WSe2 flakes, limiting scalability.
- Understanding doping effects on channel mobility and contact resistance in CVD-grown WSe2 is essential.
Purpose of the Study:
- To investigate tungsten oxide (WO) conversion as a doping method for CVD-grown WSe2 films.
- To assess the impact of WO conversion doping on device performance, including mobility and resistance.
- To demonstrate the general applicability of WO conversion for tuning threshold voltage in various low-dimensional FETs.
Main Methods:
- Utilized chemical vapor deposition (CVD) to grow WSe2 films.
- Applied WO conversion for doping WSe2 devices.
- Employed Technology Computer-Aided Design (TCAD) simulations to model the doping mechanism.
Main Results:
- Trilayer WSe2 devices achieved a median field-effect mobility of 65 cm²/V·s after WO conversion.
- Demonstrated top-gated p-type metal-oxide-semiconductor field-effect transistors (p-MOSFETs) using self-aligned WO conversion.
- Achieved a 250-fold enhancement in on-current with a subthreshold swing of 80 mV/dec in WSe2 p-MOSFETs.
Conclusions:
- WO conversion is an effective doping technique for CVD-grown WSe2, improving device performance.
- The method allows for precise threshold voltage tuning in both n-type and p-type FETs.
- This approach offers a viable pathway for developing future logic devices utilizing low-dimensional materials.
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