Analyzing the Impact of Gate Oxide Screening on Interface Trap Density in SiC Power MOSFETs Using a Novel...

Area of Science:

• Materials Science
• Semiconductor Physics
• Electrical Engineering

Background:

• Characterizing interface trap density (Dit) near the conduction band edge in 4H-Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) is crucial for device performance and reliability.
• Existing Dit extraction methods are often complex, requiring specialized equipment and detailed device fabrication knowledge, limiting their use for commercial device analysis.

Purpose of the Study:

• To introduce a novel, simplified temperature-triggered threshold voltage shift (T3VS) method for analyzing energy-dependent Dit distribution in commercial 4H-SiC MOSFETs.
• To compare the Dit levels in planar and trench gate 4H-SiC MOSFETs.
• To investigate the impact of a room-temperature gate oxide screening method (SWAP) on Dit distribution.

Main Methods:

• Utilized the temperature-triggered threshold voltage shift (T3VS) technique, which relies solely on device transfer characteristics.
• Applied T3VS to commercial 1.2 kV 4H-SiC MOSFETs with both planar and trench gate structures.
• Examined the effect of the screening with adjustment pulse (SWAP) methodology on Dit in planar MOSFETs using the T3VS method.

Main Results:

• The T3VS method provides a straightforward approach to Dit analysis without needing complex instrumentation or prior device information.
• Trench gate 4H-SiC MOSFETs exhibit significantly lower interface trap density (Dit) compared to planar gate devices.
• The SWAP screening technique was found to be aggressive, potentially introducing new defect states near the conduction band edge.

Conclusions:

• The T3VS method offers a practical and accessible tool for evaluating Dit in commercial 4H-SiC MOSFETs.
• Trench gate structures are superior to planar structures in terms of Dit, leading to enhanced reliability and efficiency.
• Careful optimization of the SWAP screening process is necessary to avoid introducing detrimental defects and ensure device reliability.