Wafer-scale uniformity improvement of Dolan-bridge Josephson junction by shadow evaporation bias correction

One of the practical limitations of solid-state superconducting quantum processors is the collision of the qubit resonance frequencies, caused by their deviation from the design specifications due to the low reproducibility in qubit fabrication. Josephson junction 100 nm-scale nonlinear inductance of the qubits still suffers from Dolan-bridge shadow evaporation process. Here, we report on a robust wafer-scale Al/AlO_x/Al Dolan-bridge Josephson junction (JJ) process using preliminary shadow evaporation bias resist mask correction and comprehensive oxidation optimization. We introduce a topology correction model for two-layer resist mask biasing at a wafer-scale, which takes into account an evaporation source geometry. It results in Josephson junction area variation coefficient ([Formula: see text]) improvement down to 1.1% for the critical dimensions from 130 × 170 nm² to 130 × 670 nm² over 70 × 70 mm² (49 cm²) wafer working area. Next, we investigate JJ oxidation process (oxidation method, pressure and time) and its impact on the room temperature resistance reproducibility. Finally, we combine both shadow evaporation bias correction and oxidation best practices for 4-inch wafers, improving [Formula: see text] down to 6.0/5.2/4.1% for 0.025 µm² JJ area and 4.0/3.4/2.3% for 0.090 µm² JJ area for 49/25/16 cm² wafer working area correspondingly. The proposed model and oxidation method can be useful for robust wafer-scale superconducting quantum processors fabrication.