A Stepped-Spacer FinFET Design for Enhanced Device Performance in FPGA Applications

Area of Science:

• Semiconductor device physics
• Advanced transistor architectures
• Nanoscale electronics

Background:

• Traditional MOSFETs face limitations at sub-10 nm scales due to short-channel effects and gate leakage.
• FinFETs, particularly junctionless variants on SOI, offer enhanced electrostatic control for scaled nodes.
• There is a need for improved transistor designs to meet the demands of modern integrated circuits.

Purpose of the Study:

• To propose and evaluate a novel Stepped-Spacer Structured FinFET (S³-FinFET).
• To investigate the S³-FinFET's performance enhancements using advanced simulation techniques.
• To assess the suitability of the S³-FinFET for applications like Field-Programmable Gate Arrays (FPGAs).

Main Methods:

• Development of a novel S³-FinFET architecture with a three-layer HfO₂/Si₃N₄/HfO₂ spacer.
• Utilizing 2D Technology Computer-Aided Design (TCAD) simulations for device evaluation.
• Analysis of key performance metrics including transfer/output characteristics, ON/OFF ratio, subthreshold swing (SS), and drain-induced barrier lowering (DIBL).

Main Results:

• The S³-FinFET demonstrates significantly improved electrostatic control and reduced parasitic effects.
• Key performance metrics show substantial enhancements in leakage current suppression and high-frequency operation.
• Simulations indicate superior subthreshold swing (SS) and drain-induced barrier lowering (DIBL) compared to conventional designs.

Conclusions:

• The S³-FinFET architecture offers a promising solution for overcoming limitations in deeply scaled transistors.
• The proposed design exhibits enhanced performance characteristics crucial for power-efficient and high-speed electronic applications.
• The S³-FinFET is particularly well-suited for Field-Programmable Gate Arrays (FPGAs) due to its improved speed and signal integrity.