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Published on: March 25, 2014
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Hardware implementation of FPGA-based spiking attention neural network accelerator.
Shiyong Geng1, Zhida Wang1, Zhipeng Liu1
1Institute of Integrated Circuits, Zhongyuan University of Technology, Zhengzhou, China.
Peerj. Computer Science
|September 24, 2025
Summary
This study introduces a lightweight Spiking Efficient Attention Neural Network (SeaSNN) accelerator for energy-efficient handwritten digit recognition on FPGAs. The SeaSNN achieves high accuracy and speed, making it suitable for resource-constrained applications.
Area of Science:
- Artificial Intelligence
- Computer Engineering
- Neuroscience
Background:
- Spiking Neural Networks (SNNs) offer biological plausibility and energy efficiency.
- Field Programmable Gate Arrays (FPGAs) present resource constraints for SNN numerical recognition.
Purpose of the Study:
- To propose a lightweight SeaSNN accelerator addressing FPGA resource limitations.
- To enhance SNN accuracy and recognition speed for handwritten digit recognition.
Main Methods:
- Developed a four-layer SeaSNN architecture.
- Integrated a Spiking Efficient Channel Attention Mechanism (SECA) for accuracy improvement.
- Optimized circuit parallelism using loop unrolling, pipelining, and array partitioning.
Main Results:
- Achieved 93.73% accuracy on MNIST dataset with the base SeaSNN.
- Increased accuracy to 94.28% with the SECA module.
- Implemented on FPGA, achieving 0.000401s/frame inference speed and 0.42 TOPS/W power efficiency at 200 MHz.
Conclusions:
- The SeaSNN accelerator provides a low-power, high-precision, and fast solution for handwritten digit recognition.
- Demonstrated suitability for resource-constrained environments and real-time applications.
