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Updated: Jan 14, 2026

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics
Published on: August 28, 2018
Sub-5 nm monolayer SnNX (X = Cl, Br)-based homogeneous CMOS devices
Yan-Dong Guo1,2, Zhi-Peng Huan1, Yu-Ting Guo1
1College of Electronic and Optical Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210046, China. yandongguo@njupt.edu.cn.
Abstract:
For next-generation CMOS electronics beyond silicon, the pursuit of channel materials capable of achieving symmetrical performance for n- and p-type devices, while supporting extreme device scaling, is of fundamental importance. Monolayer SnNX (X = Cl, Br) has emerged as a promising candidate, owing to its atomically thin structure and high carrier mobilities for both electrons and holes. Using first-principles calculations, the performance limits of sub-5 nm-Lg double-gated monolayer SnNX (X = Cl, Br) metal-oxide semiconductor field-effect transistors (MOSFETs) are explored. It is found that SnNX MOSFETs can meet the International Technology Roadmap for Semiconductors (ITRS) 2028 requirements for both high-performance (HP) and low-power (LP) applications, even at a reduced Lg of 3 nm. Notably, n-type SnNX MOSFETs with Lg = 5 nm exhibit ultra-high ON-state currents, even reaching 4533 μA μm-1, which surpass those of most reported monolayer MOSFETs. In addition, the key performance metrics, i.e., ON-state current, subthreshold swing, delay time, total capacitance and power-delay product, indicate high symmetry between n- and p-type devices. These findings highlight the potential of SnNX (X = Cl, Br) monolayers as next-generation channel materials for building CMOS integrated circuits in the post-silicon era.

