Ultra-compact scalable mode demultiplexers for high-speed optical interconnects via GPU-accelerated inverse design

We present the inverse-designed and experimental validation of ultra-compact silicon photonic mode demultiplexers supporting two- and four-mode operation on a 220 nm SOI platform. By combining pixel-level topology optimization with a GPU-accelerated full-wave adjoint solver, we reduce device footprints to 4 μm × 1.2 μm and 5.4 μm × 2.7 μm, achieving convergence in just 7 h and 27 h, respectively. Both fabricated devices exhibit insertion loss below 1 dB and crosstalk below -13 dB at the wavelength of 1550 nm, outperforming previous inverse-designed counterparts. High-speed transmission experiments using 50 Gb/s OOK and 100 Gb/s PAM4 demonstrate error-free performance with bit error rates below the HD-FEC threshold. This work establishes a scalable pathway for exabit-scale mode-division multiplexing in next-generation photonic interconnects.