A Scalable 1024-Channel Ultra-Low-Power Spike Sorting Chip with Event-Driven Detection and Spatial Clustering

Area of Science:

• Neurotechnology
• Integrated Circuit Design
• Computational Neuroscience

Background:

• Brain-computer interfaces (BCIs) face power and scalability challenges for large-scale neural recording.
• Existing spike sorting methods often demand high data bandwidth and processing power.
• Neural signal distortion and probe drift can impact the accuracy of spike sorting.

Purpose of the Study:

• To develop an ultra-low-power, 1024-channel spike sorting chip for efficient large-scale neural recording.
• To address power and scalability constraints in BCIs.
• To enhance spike sorting robustness against signal distortion and probe drift.

Main Methods:

• Integration of a compressive Analog-to-Digital Converter (ADC) and a two-stage, event-driven spike detector.
• Utilizing spatial features from high-density microelectrode arrays (MEAs) for improved cluster separability.
• Employing a modified self-organizing map algorithm for on-chip spatial clustering with minimal memory access.

Main Results:

• Achieved ultra-low power consumption (74 nW/channel) and small area (0.00029 mm²/channel) in 40 nm CMOS.
• Demonstrated over 1000x data compression.
• Validated competitive accuracy and robust drift tracking on datasets with up to 500 neurons, outperforming state-of-the-art solutions in data bandwidth, processing, and power demands.

Conclusions:

• The developed chip offers a highly scalable and power-efficient solution for large-scale neural recording in BCIs.
• Event-driven processing and spatial clustering significantly reduce computational and memory requirements.
• The design provides robust spike sorting performance, even with challenging signal conditions and planar MEAs.