Hybrid-gate MoS₂ 2T0C DRAM for low-power multi-bit storage with high linearity

Area of Science:

• Materials Science
• Electrical Engineering
• Computer Engineering

Background:

• Two-transistor, zero-capacitor (2T0C) DRAM is crucial for high-performance computing due to its density and low power.
• Conventional 2D semiconductor-based 2T0C DRAM faces challenges like reduced read current and increased power consumption at low write voltages.

Purpose of the Study:

• To address limitations in conventional 2D 2T0C DRAM.
• To propose a hybrid-gate structure for enhanced performance.

Main Methods:

• Developed a hybrid-gate MoS2 2T0C DRAM using Au-gate and Al-gate transistors.
• Integrated a 32x32 MoS2 2T0C DRAM circuit.

Main Results:

• Achieved >100 s retention time.
• Reduced minimum write voltage to 0.2 V, enabling 3-bit storage.
• Demonstrated image storage and readout with <5% bit error rate after 600 s.

Conclusions:

• The hybrid-gate MoS2 2T0C DRAM shows significant potential for high-density, low-power memory.
• This technology addresses key challenges in conventional 2D DRAM.
• The demonstrated circuit performance highlights its viability for future memory applications.