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Dual-Modulated Vertically Stacked Transistors With Fully Laminated Plate-Type Architecture Featuring Nanoscale

Goeun Pyo1, Su Jin Heo2, Jeonggyun Jang1

  • 1Department of Electrical Engineering and Computer Science (EECS), Daegu Gyeongbuk Institute of Science and Technology (DGIST), Daegu, Republic of Korea.

Advanced Science (Weinheim, Baden-Wurttemberg, Germany)
|February 3, 2026
PubMed
Summary
This summary is machine-generated.

This study introduces a novel laminated transistor design with dual gates to enhance stability and performance in nanoscale transistors. This innovative approach significantly reduces off-state leakage, paving the way for advanced low-power electronics.

Keywords:
dual gate transistorsdual modulationgraphene transistorsnanoscale channel lengthvertical thin film transistorsvertical transistorsvertically stacked transistors

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Area of Science:

  • Semiconductor device physics
  • Materials science for electronics
  • Nanotechnology

Background:

  • Nanoscale transistors face challenges with off-state leakage and stability.
  • Traditional transistor designs limit current density due to 1D current paths.

Purpose of the Study:

  • To develop a new transistor architecture addressing nanoscale device limitations.
  • To improve performance, stability, and current density in transistors.

Main Methods:

  • A fully laminated plate-type triode electrode structure with source, drain, and gate.
  • Dual-gate control using top and bottom gates to modulate channel thickness.
  • Micro-hole patterned electrodes for gate field penetration and graphene electrodes for Fermi-level modulation.
  • Integration of a leakage blocking layer to suppress carrier injection.

Main Results:

  • Achieved low off-state current (≈10-12 A) and high on/off-current ratio (>106).
  • Delivered high output currents under low-voltage operation (1 mA cm-2 at 0.1 V, 50 mA cm-2 at 1 V).
  • Maintained near-zero threshold voltage (VTH) despite nanoscale channel length.
  • Demonstrated excellent reliability against bias stress and light due to a fully encapsulated channel.

Conclusions:

  • The laminated vertical design with dual-gate control effectively enhances nanoscale transistor stability.
  • This architecture shows potential for next-generation low-power logic, memory, and flexible electronics.