3-Tier CFET 6T-SRAM with 2D-TMDs channels for Angstrom technology node.

Area of Science:

• Semiconductor device physics
• Materials science
• Computer engineering

Background:

• Conventional Static Random-Access Memory (SRAM) scaling faces physical and area limitations.
• Novel device architectures are crucial for advancing computing technologies.
• 2D Transition Metal Dichalcogenides (TMDs) offer promising channel material properties.

Purpose of the Study:

• To propose and evaluate a novel 3-Tier 6T-SRAM cell.
• To leverage a vertically stacked Complementary FET (CFET) architecture with 2D TMDs.
• To assess the performance benefits in terms of area, power, and speed.

Main Methods:

• Design and simulation of a 3-Tier CFET SRAM cell architecture.
• Integration of 2D TMDs as channel materials.
• Systematic adjustment of nanosheet stack ratios (PU: PD: PG) for optimization.
• Performance evaluation including cell area, capacitance, write energy, read-access time, and Energy-Delay Product (EDP).

Main Results:

• Achieved a 29.5% reduction in cell area compared to conventional 2-Tier structures.
• Reduced internal-node capacitance by 13-22%, leading to >39% lower write energy.
• Optimized design (2P4N + 3N_Access) improved read-access time by 11.9%.
• Demonstrated a 24.9% reduction in the Energy-Delay Product (EDP), indicating enhanced efficiency.

Conclusions:

• The proposed 3-Tier CFET SRAM architecture with 2D TMD channels offers significant miniaturization and performance improvements.
• This approach provides a viable pathway for developing high-density, high-performance, and energy-efficient SRAM.
• The technology is suitable for future high-performance computing and low-power mobile applications.