Scaling challenges and engineering approaches for oxide semiconductor FETs toward display and memory systems

Oxide semiconductors (OSs) are expanding their applicability as a field-effect transistor (FET) platform to meet distinct requirements in both display and memory applications. In display technologies, particularly extended reality (XR)-oriented high-resolution systems, the need to reduce the footprint of in-pixel transistors has driven the adoption of short-channel device designs. In parallel, the inherently low off-state current of OSs has enabled their use in capacitor-less memory architectures, such as two-transistor zero-capacitor (2T0C) DRAM, in which charge retention must be maintained without a dedicated storage capacitor. As these memory architectures pursue aggressive footprint reduction for high-density integration, OS-based transistors are increasingly required to operate under short-channel and thin-channel conditions. As channel length and thickness decrease, device characteristics become increasingly sensitive to defects generated during fabrication and operation-induced degradation, resulting in pronounced variability and reliability challenges in scaled devices. These effects are strongly coupled under short-channel and thin-channel conditions and cannot be adequately mitigated through dimensional scaling alone. This review examines channel scaling in OS FETs from both short-channel and thin-channel perspectives, emphasizing the interplay between defect formation during fabrication and failure mechanisms during device operation. By comparing representative planar, self-aligned, vertical, and three-dimensional device architectures through the lens of channel scaling, this work highlights chemical and structural engineering strategies for footprint reduction and leakage suppression and discusses pathways toward advanced device platforms for high-resolution displays and capacitor-less memory applications.