Scaling challenges and engineering approaches for oxide semiconductor FETs toward display and memory systems

Area of Science:

• Materials Science
• Electrical Engineering
• Semiconductor Physics

Background:

• Oxide semiconductors (OSs) are crucial for field-effect transistor (FET) platforms in displays and memory.
• Short-channel designs are needed for compact in-pixel transistors in high-resolution displays (e.g., extended reality).
• OSs enable capacitor-less memory (e.g., 2T0C DRAM) due to low off-state current, requiring charge retention without storage capacitors.

Purpose of the Study:

• To review channel scaling in OS FETs, focusing on short-channel and thin-channel effects.
• To analyze the interplay between fabrication defects and operational degradation in scaled OS devices.
• To explore chemical and structural engineering strategies for advanced OS FET platforms.

Main Methods:

• Comparative analysis of planar, self-aligned, vertical, and 3D OS FET architectures.
• Examination of defect formation during fabrication processes.
• Investigation of device operation-induced degradation mechanisms.

Main Results:

• Device characteristics in scaled OS FETs are highly sensitive to fabrication defects and operational degradation.
• Variability and reliability challenges intensify under short-channel and thin-channel conditions.
• Dimensional scaling alone is insufficient to mitigate these challenges.

Conclusions:

• Advanced chemical and structural engineering are essential for footprint reduction and leakage suppression in OS FETs.
• Addressing defect formation and failure mechanisms is key to developing reliable scaled devices.
• New device architectures and engineering strategies are needed for high-resolution displays and dense capacitor-less memory.