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Updated: Oct 9, 2026

Electric-field Control of Electronic States in WS2 Nanodevices by Electrolyte Gating
Published on: April 12, 2018
Wafer-scale synthesis of WSe2 for high-performance p-type top-gated transistors and logic circuits
Jonggyu Choi1, Hayoung Kim1, Seungsoo Kim1
1School of Electrical and Electronic Engineering, Yonsei University, 50 Yonsei-ro, Seoul 03722, Republic of Korea.
Abstract:
Two-dimensional (2D) transition metal dichalcogenides (TMDs) offer a promising pathway for next-generation electronics due to their exceptional electrical characteristics at atomically thin thickness. Nevertheless, the realization of high-quality p-type 2D-FETs remains a significant challenge for CMOS device integration due to surface damage and unintended n-doping induced during dielectric deposition. In this work, we report the wafer-scale synthesis of p-type WSe2 films using metal-organic chemical vapor deposition and the fabrication of top-gate p-FETs through a buffer layer strategy, which provides superior electrostatic control and channel stability. The transistors exhibit excellent p-type performance, achieving a hole mobility of 10.49 ± 2.35 cm2V-1 s-1 with on/off current ratio exceeding 109. By leveraging the process's scalability, which ensures uniform and damage-free fabrication, we successfully produced reliable wafer-scale PMOS logic circuits. This study provides a scalable, damage-free integration solution for 2D electronics, paving the way for the practical realization of all 2D-based high-density electronics and circuits.
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