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IEEE Transactions on Neural Networks and Learning Systems
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November 29, 2023
A Low-Latency DNN Accelerator Enabled by DFT-Based Convolution Execution Within Crossbar Arrays
Hasita Veluri, Umesh Chand, Chun-Kuei Chen, et al.
IEEE Transactions on Neural Networks and Learning Systems
|
October 20, 2021
A Low-Power DNN Accelerator Enabled by a Novel Staircase RRAM Array
Hasita Veluri, Umesh Chand, Yida Li, et al.
Nature Communications
|
November 16, 2019
All WSe<sub>2</sub> 1T1R resistive RAM cell for future monolithic 3D embedded memory integration
Maheswari Sivan, Yida Li, Hasita Veluri, et al.
Nature Communications
|
June 1, 2022
Wafer-scale solution-processed 2D material analog resistive memory array for memory-based computing
Baoshan Tang, Hasita Veluri, Yida Li, et al.
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of 1
Search research articles
Search
Showing results (1-10 of 4) with videos related to
Sort By:
Page
of 1
IEEE Transactions on Neural Networks and Learning Systems
|
November 29, 2023
A Low-Latency DNN Accelerator Enabled by DFT-Based Convolution Execution Within Crossbar Arrays
Hasita Veluri, Umesh Chand, Chun-Kuei Chen, et al.
IEEE Transactions on Neural Networks and Learning Systems
|
October 20, 2021
A Low-Power DNN Accelerator Enabled by a Novel Staircase RRAM Array
Hasita Veluri, Umesh Chand, Yida Li, et al.
Nature Communications
|
November 16, 2019
All WSe<sub>2</sub> 1T1R resistive RAM cell for future monolithic 3D embedded memory integration
Maheswari Sivan, Yida Li, Hasita Veluri, et al.
Nature Communications
|
June 1, 2022
Wafer-scale solution-processed 2D material analog resistive memory array for memory-based computing
Baoshan Tang, Hasita Veluri, Yida Li, et al.
Page
of 1