Tao Liu
8PUBLICATIONS
6CO-AUTHORS
Get your video featured.
Publish with JoVEGet your video featured.
Publish with JoVE
Publications (8)
Sort by Publication Date:
|Mar 13, 2026
3-Levels Vertically Stacked Si Nanosheet GAA pFETs with Low-Temperature Interface Treatment for Cryogenic Application.Lewen Qian, Tao Liu, Meicheng Liao
|Jan 27, 2026
Feature Comparison and Process Optimization of Multiple Dry Etching Techniques Applied in Inner Spacer Cavity Formation of GAA NSFET.Meng Wang, Xinlong Guo, Ziqiang Huang
|Jun 13, 2024
A Comprehensive Study of NF3-Based Selective Etching Processes: Application to the Fabrication of Vertically Stacked Horizontal Gate-All-around Si Nanosheet Transistors.Xin Sun, Jiayang Li, Lewen Qian
|Sep 28, 2023
A Buried Thermal Rail (BTR) Technology to Improve Electrothermal Characteristics of Complementary Field-Effect Transistor (CFET).Zhecheng Pan, Tao Liu, Jingwen Yang
|Jun 28, 2023
A Novel Scheme for Full Bottom Dielectric Isolation in Stacked Si Nanosheet Gate-All-Around Transistors.Jingwen Yang, Ziqiang Huang, Dawei Wang
Pageof 2