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Fabrication of Gate-tunable Graphene Devices for Scanning Tunneling Microscopy Studies with Coulomb Impurities
Published on: July 24, 2015
Synthesis of graphene on silicon dioxide by a solid carbon source
Jens Hofrichter1, Bartholomäus N Szafranek, Martin Otto
1Advanced Microelectronic Center Aachen, AMO GmbH, Otto-Blumenthal-Strasse 25, Aachen, Germany. jho@zurich.ibm.com
This study presents a novel method for mass-producing polycrystalline graphene on silicon dioxide substrates. The process involves solid-state dissolution and segregation, enabling CMOS-compatible fabrication without transfer steps.
Area of Science:
- Materials Science
- Nanotechnology
- Solid-State Physics
Background:
- Graphene synthesis is crucial for advanced electronics.
- Current methods often involve complex transfer steps, limiting scalability.
- Developing direct fabrication methods on insulating substrates is highly desirable.
Purpose of the Study:
- To develop a novel, scalable method for graphene fabrication on silicon dioxide.
- To characterize the morphology and electrical properties of the synthesized graphene.
- To demonstrate the feasibility of using CMOS-compatible processes.
Main Methods:
- Fabrication via solid-state dissolution of silicon carbide and nickel thin films.
- Rapid thermal annealing for carbon dissolution and segregation.
- Wet etching of nickel to transfer graphene to silicon dioxide.
- Characterization using Scanning Tunneling Microscopy (STM) and Raman spectroscopy.
- Raman mapping for morphological analysis.
- Fabrication of devices for electrical measurements.
Main Results:
- Successful fabrication of polycrystalline graphene over the entire nickel surface.
- Micrometer-size graphene grains observed via Raman mapping.
- Electrical characterization showed modulation of transfer current by backgate electric fields.
- Demonstrated a transfer-free graphene fabrication process.
Conclusions:
- The presented method enables mass fabrication of polycrystalline graphene on silicon dioxide.
- The process is compatible with Complementary Metal-Oxide-Semiconductor (CMOS) manufacturing.
- This approach offers a scalable route for graphene integration in electronic devices.
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