An Integrated Implantable Stimulator That is Fail-Safe Without Off-Chip Blocking-Capacitors.

Area of Science:

• Biomedical Engineering
• Electrical Engineering
• Neuroscience

Background:

• Implantable neural stimulators are crucial for functional electrical stimulation (FES).
• Conventional FES systems require bulky off-chip blocking-capacitors, limiting miniaturization.
• Existing designs face challenges in achieving fail-safe operation and reducing power consumption.

Purpose of the Study:

• To develop a miniaturized, fail-safe neural stimulator chip.
• To introduce novel techniques for reducing the size and power consumption of the stimulator output stage.
• To enable on-chip integration of safety components for implantable devices.

Main Methods:

• A new single-step current generator circuit using voltage-controlled resistors.
• A high-frequency current-switching (HFCS) technique for blocking-capacitor safety protection.
• Fabrication of a prototype four-channel neural stimulator chip in 1-mum silicon-on-insulator CMOS technology.

Main Results:

• The stimulator chip is fail-safe under single-fault conditions.
• Capacitance requirement for safety protection reduced to the picofarad range, enabling on-chip integration.
• Demonstrated successful recordings of action potentials and strength-duration curves from frog sciatic nerve.
• Achieved low power consumption (200 μW at 6V for 1mA, 20Hz stimulation) and small silicon area (0.38 mm² per channel).

Conclusions:

• The novel techniques enable the development of highly miniaturized and power-efficient neural stimulator chips.
• The HFCS technique provides effective on-chip safety protection, crucial for implantable FES systems.
• The prototype chip validates the feasibility and performance of the proposed design for neural stimulation.