A 155 μ W 88-dB DR discrete-time ∆Σ modulator for digital hearing aids exploiting a summing SAR ADC quantizer

Area of Science:

• Electrical Engineering
• Signal Processing
• Integrated Circuit Design

Background:

• Digital hearing aids require efficient analog-to-digital converters (ADCs) for processing audio signals.
• Traditional delta-sigma modulators (∆ΣM) often face challenges with power consumption and circuit complexity.
• Feed-forward (FF) ∆ΣM topologies necessitate analog addition, which can introduce attenuation and require amplifiers.

Purpose of the Study:

• To present a novel low-power switched-capacitor ∆Σ modulator for digital hearing-aid applications.
• To introduce a summing successive approximation (SAR) architecture that integrates analog addition and multi-bit quantization.
• To reduce the power consumption and circuit complexity of ∆Σ modulators.

Main Methods:

• Implementation of a switched-capacitor ∆Σ modulator with a novel summing SAR architecture in 0.18-μm CMOS technology.
• The summing SAR performs analog addition and multi-bit quantization simultaneously, avoiding input signal attenuation and the need for amplifiers.
• Utilizing passive addition combined with SAR quantization to decrease modulator complexity and power usage.

Main Results:

• The prototype modulator achieved a dynamic range of 88 dB within a 10 kHz bandwidth.
• The device consumed only 155 μW from a 1.8 V power supply.
• The summing SAR ADC quantizer demonstrated a calculated power saving of 40% compared to conventional multi-bit FF ∆ΣM designs.

Conclusions:

• The proposed summing SAR architecture offers a significant reduction in power consumption for digital hearing-aid ADCs.
• The integration of analog addition and quantization in the summing SAR simplifies modulator design and enhances efficiency.
• This approach provides a promising solution for developing more power-efficient and less complex hearing-aid devices.